Porting - Peripheral Interfaces
1. I2C
- Four I2C groups are in use on the APLUX board. View the corresponding nodes with the following command:
bash
sh-5.1# ls -l /sys/bus/i2c/devices/i2c*
total 0
lrwxrwxrwx 1 root root 0 Jun 5 22:37 i2c-0 -> ../../../../devices/platform/soc/9c0000.qcom,qupv3_i2c_geni_se/988000.i2c/i2c-0
lrwxrwxrwx 1 root root 0 Jun 5 22:37 i2c-1 -> ../../../../devices/platform/soc/9c0000.qcom,qupv3_i2c_geni_se/98c000.i2c/i2c-1
lrwxrwxrwx 1 root root 0 Jun 5 22:37 i2c-2 -> ../../../../devices/platform/soc/9c0000.qcom,qupv3_i2c_geni_se/990000.i2c/i2c-2
lrwxrwxrwx 1 root root 0 Jun 5 22:37 i2c-3 -> ../../../../devices/platform/soc/ac0000.qcom,qupv3_1_geni_se/a90000.i2c/i2c-3
lrwxrwxrwx 1 root root 0 Jun 5 22:37 i2c-4 -> ../../../../devices/platform/soc/ae90000.qcom,dp_display/i2c-4Corresponding Hardware Information
| Device Name | Base Address | GPIO | Device Tree Node |
|---|---|---|---|
| i2c-0 | 988000 | 20/21 | qupv3_hub_i2c2 |
| i2c-1 | 98c000 | 22/23 | qupv3_hub_i2c3 |
| i2c-2 | 990000 | 4/5 | qupv3_hub_i2c4 |
| i2c-3 | a90000 | 44/45 | qupv3_se4_i2c |
Modification Example: RTC Chip INS5830B
The I2C pins used are GPIO20 and GPIO21.
kalama-pinctrl.dtsi configures the I2C muxing for these two pins:
qupv3_hub_i2c2_pins: qupv3_hub_i2c2_pins {
qupv3_hub_i2c2_sda_active: qupv3_hub_i2c2_sda_active {
mux {
pins = "gpio20";
function = "i2chub0_se2_l0";
};
config {
pins = "gpio20";
drive-strength = <2>;
bias-pull-up;
qcom,i2c_pull;
};
};
qupv3_hub_i2c2_scl_active: qupv3_hub_i2c2_scl_active {
mux {
pins = "gpio21";
function = "i2chub0_se2_l1";
};
config {
pins = "gpio21";
drive-strength = <2>;
bias-pull-up;
qcom,i2c_pull;
};
};
};kalama-qupv3.dtsi configures the device tree node for qupv3_hub_i2c2, referencing the above pinctrl:
qupv3_hub_i2c2: i2c@988000 {
compatible = "qcom,i2c-geni";
reg = <0x988000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk", "core-clk";
clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
interconnect-names = "qup-core", "qup-config";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_hub_i2c2_sda_active>, <&qupv3_hub_i2c2_scl_active>;
pinctrl-1 = <&qupv3_hub_i2c2_sleep>;
qcom,i2c-hub;
status = "disabled";
};kalamap-rb5-gen2.dtsi configures the RTC device tree node under qupv3_hub_i2c2:
&qupv3_hub_i2c2 {
status = "ok";
#address-cells = <1>;
#size-cells = <0>;
ins5830b: ins5830b@32 {
compatible = "dptel,rtc-ins5830b";
reg = <0x32>;
pinctrl-names = "default";
pinctrl-0 = <&ins5830b_int_default>;
interrupt-parent = <&tlmm>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
};
};2. SPI
- Four SPI groups are in use on the APLUX board. View the corresponding nodes with the following command:
bash
sh-5.1# ls -l /sys/bus/spi/devices/
total 0
lrwxrwxrwx 1 root root 0 Jun 11 06:45 spi0.0 -> ../../../../devices/platform/soc/ac0000.qcom,qupv3_1_geni_se/a84000.spi/spi_master/spi0/spi0.0
lrwxrwxrwx 1 root root 0 Jun 11 06:45 spi1.0 -> ../../../../devices/platform/soc/ac0000.qcom,qupv3_1_geni_se/a88000.spi/spi_master/spi1/spi1.0
lrwxrwxrwx 1 root root 0 Jun 11 07:16 spi2.0 -> ../../../../devices/platform/soc/8c0000.qcom,qupv3_2_geni_se/888000.spi/spi_master/spi2/spi2.0
lrwxrwxrwx 1 root root 0 Jun 11 07:16 spi3.0 -> ../../../../devices/platform/soc/8c0000.qcom,qupv3_2_geni_se/894000.spi/spi_master/spi3/spi3.0Corresponding Hardware Information
| Device Name | Base Address | GPIO | Device Tree Node |
|---|---|---|---|
| spi0.0 | a84000 | 32/33/34/35 | qupv3_se1_spi |
| spi1.0 | a88000 | 36/37/38/39 | qupv3_se2_spi |
| spi2.0 | 888000 | 64/65/66/67 | qupv3_se10_spi |
| spi3.0 | 894000 | 80/81/82/83 | qupv3_se13_spi |
Modification Example: CAN Chip MCP2518
The SPI pins used are GPIO32 ~ GPIO35 (SE1's QUP type is configured as SPI in TZ).
kalama-pinctrl.dtsi configures the QUP muxing for these pins:
qupv3_se1_spi_pins: qupv3_se1_spi_pins {
qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
mux {
pins = "gpio32";
function = "qup1_se1_l0";
};
config {
pins = "gpio32";
drive-strength = <6>;
bias-disable;
};
};
qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
mux {
pins = "gpio33";
function = "qup1_se1_l1";
};
config {
pins = "gpio33";
drive-strength = <6>;
bias-disable;
};
};
qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
mux {
pins = "gpio34";
function = "qup1_se1_l2";
};
config {
pins = "gpio34";
drive-strength = <6>;
bias-disable;
};
};
qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
mux {
pins = "gpio35";
function = "qup1_se1_l3";
};
config {
pins = "gpio35";
drive-strength = <6>;
bias-disable;
};
};
};kalama-qupv3.dtsi configures the device tree node for qupv3_se1_spi:
qupv3_se1_spi: spi@a84000 {
compatible = "qcom,spi-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
<&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
status = "disabled";
};